1. Field of the Invention
This invention generally relates to electronic memories and more specifically to synchronous Static Random Access Memory design.
2. Description of Related Art
Static Random Access Memory (SRAM) is a type of electronic memory that is faster and more reliable than the more common Dynamic Random Access Memory (DRAM). The term "static" is derived from the fact that SRAM does not need to be refreshed like DRAM. As long as SRAM memory is supplied power, it will retain its memory.
SRAM is often used as cache memory. Some cache memories are built into microprocessors. The Intel.RTM. 80486 microprocessor, for example, contains an 8K memory cache, and the Pentium.RTM. microprocessor contains a 16K cache. Such internal caches are often called Level 1 (L1) caches. Many modern PCs also come with external cache memory, called Level 2 (L2) cache. These caches reside between the CPU and the DRAM. Like L1 caches, L2 caches are composed of SRAM but are typically much larger.
Regardless of how an SRAM chip is implemented, the architecture is somewhat standard. All SRAM chips contain an array of memory cells. A memory cell stores a single bit of information (1 or 0). Peripheral circuits control how each memory cell is accessed. A unique address refers to either a single bit or a group of bits, depending upon the architecture of the SRAM chip. All references to a "set of memory cells" shall mean the set of bits stored in one address location, regardless of whether the number of bits is singular or plural.
Synchronous SRAM uses a clock signal to time the phases of operation of the SRAM circuit. For active-high logic circuits, the pre-charge phase ("PC phase") is performed during the high portion of the clock signal and the access phase ("AC phase") during the low portion. The phases of an active-low circuit are performed in the opposite clock states. Although the circuits described herein will assume active-high logic, those skilled in the art will be able to apply the concepts to either active-high or active-low circuitry.
During the PC phase, the memory array pre-charges, the address is decoded and the decision of whether to read or write is made. The AC phase is when the actual reading or writing to the memory cell is performed. Since both phases are necessary, only one complete read or write operation can be performed during a full clock period for a standard six transistor SRAM chip.
The cost effectiveness of synchronous SRAM depends partly upon the speed of the clock signal. A system with a clock signal that remains in its high state for longer than is needed to complete the PC phase is inefficient. Similarly, it is inefficient for an SRAM chip to remain in its AC phase for longer than is required while the clock signal is low. The speed of a system clock is usually selected based on the requirements of the processor rather than being selected to optimize operation of an SRAM chip.
Direct Memory Access (DMA) is a technique for transferring data from main memory to a CPU without passing it through a memory management system. A DMA request could occur at either the first half or the second half of a clock cycle. If a DMA request were received in the second half of a clock cycle, a prior art synchronous SRAM chip would not be able to process the request until the next clock cycle.
Additionally, since the majority of SRAM chips are single port chips that only allow one memory access at a time, the microprocessor would be required arbitrate DMA requests. The microprocessor would grant a DMA request by pausing its own use of the memory while allowing the device requesting the DMA to access the memory. Although dual port memory chips are available, they are far too large and costly to be used regularly.
What is needed is a synchronous SRAM chip that overcomes shortfalls of the SRAMs currently known in the art.